A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology

This letter presents a global resonant clocking mesh architecture utilizing backside metal layers in an 18A class technology. Rotary traveling wave oscillators are implemented to provide synchronous low-skew, low-jitter, and 50% duty cycle clocks across a graphics core. To provide dynamic frequency and voltage scaling capabilities across a wide range of operating conditions, a high-speed fractional divider is designed. The proposed architecture is implemented on a 1.6 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1.6 mm graphics core achieving FoMJ of 246 dB FoMT 190.3dBc/Hz.