ANCHOR Stream Cipher for Smart Cards FPGA-Based Implementation

Robust and efficient cryptographic solutions are essential for secure data processing and storage in resource-constrained environments such as smart cards. This paper presents the design, implementation, simulation, and analysis of the ANCHOR cryptosystem, a new stream cipher designed for limited resources environments such as smart cards. The VHDL-based implementation was developed, synthesized, and tested on a Xilinx Spartan-3 FPGA (XC3S700AN), demonstrating efficient use of FPGA resources with only 2% of slices and 1% of slice flip-flops utilized. The cryptosystem achieved a maximum operational frequency of 231.267 MHz, capable of generating an 8000-bit output in 0.0346 milliseconds. The implementation's correctness and reliability were validated through ISim and C-language simulations, ensuring consistency across different environments. After downloading the design on the target FPGA, a logic analyzer was used to measure and verify the performance of the ANCOR cryptosystem. The measurements were identical to the simulation results. The ANCHOR cryptosystem presents a compact minimal footprint, high speed, and robust security features making it an ideal candidate for highly sensitive data security applications like the Unified Citizen Smart Card (UCSC).