Improving At-Speed Test Coverage without compromising Test Time and reducing Test Cost in multi-partition SCAN Design

With constantly scaling down of the technology, the complexity of SoC becoming very high due to implementation of digital, analog and memory logic. This is imposing challenge in meeting the coverage goal for the detection of manufacturing defect post-silicon on the ATE. During the implementation of industrial SoC design with multiple partitions, the difficulty is observed to achieve the at-speed transition coverage goal (90%) on ATE with limited memory (~20MB). However, the current production pattern set requires ~250MB of ATE memory. In order to achieve the required at-speed coverage goal (90%) with existing design with less pattern count, the coverage loss is analyzed in different portions such as surrounding logic of memory, the functional ICG enable logic. With the proposed solutions to resolve the loss of coverage, the coverage goal (90%) is met well within tester vector storage memory requirement with production pattern set. In addition, the disabling of the low power feature of the compression logic have further reduced the pattern count and hence, it decreased of the total test time and cost without compromising the peak and average power budget. Furthermore, the novel architecture is proposed with the usage of with minimal test area overhead to cover the faults in the interface logic between partitions which further leads to improvement in at-speed coverage.