Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs

An Arbiter PUF (APUF) is a useful hardware security primitive. However, FPGA-based design and implementation of APUF circuits with superior values of quality metrics have proven to be extremely challenging. In this work, we have designed a novel 64-bit APUF which is "robust-by-construction", i.e., it has close to ideal values of quality metrics when implemented. The circuit structure and methodical implementation on a Xilinx FPGA platform ensure that the response bit is unbiased, and is dependent on intrinsic process variation alone. The effect of placement and routing tools and the choice of last-stage arbiters have been investigated in detail. Our implemented APUF achieves average Uniformity, Uniqueness, Steadiness, Min-Entropy, and Reliability (evaluated at four operating temperatures) metric values of 51.22%, 50.81%, 1.82%, 88.38%, and 99.34%, respectively. A software-based fuzzy error correction scheme is used on the responses generated at different temperatures. The design is also found to be strongly resistant to machine learning based model-building attacks, with Logistic Regression (LR) and Support Vector Machine (SVM) prediction accuracies of 51.22% and 52.61% respectively, on a dataset of 2,097,152 CRPs using additive delay models and a security analysis is performed using MLP modelling-attacks of the pypuf framework.