Reliability Enhancement of Memristor-Based Neural Networks with Fault-Injected Training

The demand for executing neural network (NN) learning and inference on edge devices is increasing. Memristor crossbar (MC) devices in neuromorphic computing (NC) provide a promising solution for accelerating NNs. However, immature fabrication technology makes faulty memristors inevitable, and the presence of stuck-at faults (SAFs) in MC devices substantially reduces the inference accuracy of NC System. The existing fault-resilient methods, which depend on mapping and retraining algorithms, cause costly and time-consuming processes with hardware overhead. This paper proposes a reliability-aware design framework for an NC system utilizing MC devices by combining fault-resilient training and IC-specific mapping. First, we apply fault-resilient training to enhance the robustness of the NN model. SAF-injected training is developed in this phase to mitigate the effects of SAFs. Then we map the weights of the trained model to MCs. The proposed framework preserves the inference accuracy without re-training, even though MCs are suffered from SAFs. Our proposed method is assessed using two different NN applications across two distinct datasets. The experimental results show that the proposed framework achieves high inference accuracy for several differently faulty MCs and enhances the reliability of NC system.

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Published
2024-12-17
DOI
https://doi.org/10.1109/ats64447.2024.10915534
Primary Topic
Advanced Memory and Neural Computing
Type
article
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Reliability Enhancement of Memristor-Based Neural Networks with Fault-Injected Training

Michiko Inoue, Ryota Eguchi, Md. Ariful Islam
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Advanced Memory and Neural Computing
article

Reliability Enhancement of Memristor-Based Neural Networks with Fault-Injected Training

Michiko Inoue, Ryota Eguchi, Md. Ariful Islam
article en

Abstract

The demand for executing neural network (NN) learning and inference on edge devices is increasing. Memristor crossbar (MC) devices in neuromorphic computing (NC) provide a promising solution for accelerating NNs. However, immature fabrication technology makes faulty memristors inevitable, and the presence of stuck-at faults (SAFs) in MC devices substantially reduces the inference accuracy of NC System. The existing fault-resilient methods, which depend on mapping and retraining algorithms, cause costly and time-consuming processes with hardware overhead. This paper proposes a reliability-aware design framework for an NC system utilizing MC devices by combining fault-resilient training and IC-specific mapping. First, we apply fault-resilient training to enhance the robustness of the NN model. SAF-injected training is developed in this phase to mitigate the effects of SAFs. Then we map the weights of the trained model to MCs. The proposed framework preserves the inference accuracy without re-training, even though MCs are suffered from SAFs. Our proposed method is assessed using two different NN applications across two distinct datasets. The experimental results show that the proposed framework achieves high inference accuracy for several differently faulty MCs and enhances the reliability of NC system.

Nara Institute of Science and Technology (JP)
Openalex Percentile: Top 74%
Advanced Memory and Neural Computing
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