A Novel Differential 12T SRAM Bit-cell Structure with Improved SNM in 16nm FinFET Technology

This paper presents an innovative 12T SRAM bit-cell design that achieves enhanced differential read and write operations at near-threshold voltages (Vth). Unlike traditional SRAM cells, the proposed design integrates inverse bit line feedback control and isolated read buffers to boost performance. Based on a modified 6T SRAM core, it adds two-bit line feedback control transistors to improve write efficiency and features separate read buffers with isolated storage nodes to enhance read margin. Simulations in 16 nm MG-FinFET technology at 0.85 V and 0.6 V show that this 12T SRAM cell surpasses the performance of 10T, 10T PPN, sensing-8T, and conventional 6T SRAM cells. It demonstrates a write static noise margin (WSNM) of 646 mV and a read static noise margin (RSNM) of 253 mV, outperforming these SRAM designs in both N-Vth and S-Vth regions. Additionally, it offers reduced static power consumption (304 pW in the S-Vth region and 82 pW in the N-Vth region) and faster read/write delays. The superior performance is attributed to the incorporation of stacked small-sized NMOS transistors in the new design.