Sleptsov net based reliable embedded system design on microcontrollers and FPGAs

We present a novel methodology of embedded systems design based on Sleptsov net (SN) formalism. We use an SN as a graphical language of concurrent programming and as a modeling language for plant specification and integrated model composition. Among the advantages, we mention the applicability of formal verification techniques for reliable embedded system design, vivid graphical language, and compatibility of the tool-chain with different classes of hardware. Composed tool-chains are supplied with our ad-hoc tools for embedded systems design on both microcontrollers and FPGAs. We develop a software SN machine for microcontrollers and a generator of Verilog programs for FPGAs. Compared to known SN machine implementations on desktop computers and GPUs, we developed an indexed sparse matrix data structure to optimize both memory usage and performance. Benchmarks on real-life Sleptsov net programs show the robustness of the approach with considerably higher performance on FPGA.