Methods and Apparatus to Support Multiple Synchronous Clocks with a Single Clock Mesh

A Clock Mesh is a structure commonly used in System-on-a-Chip (SoC) designs running at very high clock rates, typically beyond 2.0 GHz, to distribute a clock signal across a large region of a chip. The clock mesh typically is implemented using wires on two adjacent and orthogonal levels of metal in a chip, in which the wires are tied together at each point of intersection. Taps of the mesh are made as needed to service the clocking needs of logic below the mesh. A typical tap would normally service the clocking needs of an area that is in the order of 0.01 sq mm. Several taps are placed beneath the mesh to ensure coverage of the entire area of the block. In some SOC Designs, two or more synchronous clocks are needed to support logic which is placed below the clock mesh. Typically, the synchronous clocks are divided clocks. To meet the timing closure requirements of the logic, when logic of one synchronous clock drives logic associated with the other synchronous clock, it is necessary to provide precise alignment of the clocks, including precise alignment of coincident edges of the synchronous clocks. In this paper, we propose a method of supporting the requirement of multiple synchronous clocks with a single mesh and meeting the Design for Test needs of such designs.