Power Aware test methodology for Test Power hungry complex SoCs

Recent advancements in semiconductor technology nodes, makes it possible to accommodate large number of transistors in single System on Chip (SoC) to achieve intended functionality. It has always been challenging to test such highly area dense logic of SoCs at its functional/ operational speed with optimized test time and within its functional power consumption limits. ATPG is the most effective and efficient method of structurally testing the digital logic, which involves sequentially loading and un-loading of the scan chains. All design flip-flops in the SoC toggles in a random controlled fashion during ATPG test and lead to design toggle activity much beyond the functional threshold limits. The design power grid needs to be robust enough to cater to the demand current during test, otherwise this could lead to failures and yield loss in production test. Application of ATPG test is limited by average and peak power consumption of the device under test. This paper witnesses several proposed power aware test methodologies, which has contributed to minimize scan peak IR drop from more than 50% to within acceptable limit along with peak current reduced from 1A to 0.2A and contributed to nullify yield loss due to test power. Proposed power aware test methodologies are implemented in 45nm Industrial SoC designs and from volume data silicon results proves practical effectiveness of it.