Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction

Fast simulation is vital for efficient digital design, especially for safety-critical applications, where functional safety verification is paramount. However, existing gate-level event-driven simulators often encounter performance challenges attributed not only to inefficient memory access, but also to redundancy events in sequential elements during event-driven algorithms. In this paper, we introduce a memory-efficient, low-redundancy event-driven simulation framework to accelerate sequential circuit simulation. Firstly, we propose an event-based memory layout approach that fully considers memory access characteristics within and between logic levels to enhance the spatial locality of simulators. Secondly, we present an event trace approach tailored for flip-flops to reduce event redundancies that hinder simulator performance. Comparative experiments demonstrate that our proposed optimization strategies deliver an average performance improvement of 1.9× for logic simulation and 1.4× for fault simulation.