RTL design of 16-bit RISC Processor Using Vedic Mathematics

The present paper proposes a new solution for designing a 16-bit RISC microprocessor that uses the Vedic Mathematics approaches, which, in the past, have been known for providing high-performance arithmetic computations. The principal aim is to implement the Urdhva-Tiryagbhyam for implementing multiplication and subtraction operations in the processor’s ALU. This design has been tailored to improve computational power while minimizing the power consumption and complexity of the associated hardware. The proposed processor design, implemented in Verilog and synthesized on Xilinx Vivado, aims to reduce logic complexity, power consumption, and clock cycles for arithmetic operations compared to a conventional RISC processor. Simulation results show a 66.89% reduction in LUT usage, a 40.5% reduction in slice registers, and an approximate 24% reduction in power consumption for arithmetic-intensive tasks. These findings establish the proposed Vedic RISC processor as a promising solution for embedded applications requiring high speed and low power. Future work will explore extending this Vedic-based approach to multi-cycle instructions and pipeline optimization.