Optimizing LBIST Run Time for a Safety Critical SoC: A Practical Approach

One of the key benefits of using logic built-in self-test (LBIST) is that it eliminates the need for external test equipment, such as automatic test equipment (ATE), to identify faults in silicon. However, due to its target patterns non-deterministic, LBIST may not detect faults as effectively as automatic test pattern generation (ATPG) tools. For safety-critical devices (ASIL-D), which require a latent fault metric (LFM) of at least 90%, efficient LBIST implementation is essential, as it impacts boot time. This paper discusses the results of optimizing LBIST runtime for a new safety-critical device from Texas Instruments. Through various experiments and improved implementation techniques i.e., splitting ATPG chain, using optimal test point configuration etc., we achieved an approximate 88% reduction in LBIST runtime at 200 MHz.