ML Based Diagnosis for Fault Location in Digital Circuits
Fault diagnosis is crucial for pinpointing failure causes in manufactured chips, improving yield. The primary objective is to accurately narrow down potential fault locations in a circuit. However, the effectiveness of diagnosis algorithms heavily depends on the quality of the test set. If the test set fails to distinguish between fault pairs, the algorithm struggles to identify many faults. This highlights the need for a metric to quantify the diagnostic capability of test sets based on their efficacy. Traditional diagnosis methods, while accurate, face limitations due to their space and time complexity. Selecting the most suitable test set for improved diagnosis becomes challenging when multiple sets have the same fault coverage. This literature introduces a new machine learning-based diagnostic method to evaluate the diagnostic efficacy of test vectors using a Failure Catalogue, which includes failure ID, test pattern, targeted faults, expected and actual response, and failing scan and primary outputs. Four benchmark circuits are compared based on features such as the number of gates, drivers, loads, ports, faults, area, and power. The diagnostic accuracy of various machine learning models, including Random Forest, Decision Tree, K-Nearest Neighbors (KNN), and Support Vector Machine (SVM), is measured for both single and multiple fault predictions.
Authors
- Sudip Ghosh (ORCID: https://orcid.org/0000-0001-5750-2501)
- Debasis Bagchi (ORCID: https://orcid.org/0000-0001-9478-6427)
- Subhajit Chatterjee (ORCID: https://orcid.org/0000-0003-1648-6095)
- Habibur Rahaman (ORCID: https://orcid.org/0000-0003-2023-4595)
Institutions
- Indian Institute of Engineering Science and Technology, Shibpur (IN)
Publication Details
- Published
- 2024-12-17
- DOI
- https://doi.org/10.1109/ats64447.2024.10915466
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00