Preferential Fault-Tolerant based TF32 Floating Point Adder for Mission Critical Systems

TensorFloat32 (TF32) floating-point adders process machine learning and deep learning applications in mission-critical systems. The mission-critical systems operated in radiation or high-temperature working conditions. These environmental conditions may be susceptible to single-event upsets (SEUs). The SEUs will result in incorrect outcomes, which may cause system failure. SEUs can be abolished by incorporating fault-tolerant techniques into the adder circuits. However, the primary concern is the hardware overhead associated with these circuits, which leads to more delay. So, to address these challenges, propose a Preferential Fault-Tolerant (PrFT) TF32 floating-point adder. The proposed adder architecture was developed using an error-analysis approach, which involves a preferential method to select the most critical hardware for applying TMR to mitigate faults as well as to reduce hardware cost and delay. The hardware reduces the 39.97% compared to the Triple Modular Redundancy-based TF32 adder. To evaluate the performance and efficiency of the proposed work, we conducted simulations and implemented the design on a Field-Programmable Gate Array (FPGA).