High performance advanced fault model diagnosis

Scan based diagnosis is an industry proven approach to aid in identifying the root-cause of defects in silicon. ATPG fault models such as stuck-at, transition are typically used for identifying the best possible fault location(s) that explain the potential reason for tester failures. With lower technology nodes, the correlation between behavior of defects in silicon and the modeled faults is quickly declining. Opens and Shorts either internal to library cells or the cell interconnects, timing defects at a specific location or on a specific path are some examples. With the addition of these new defect types, newer and complex fault models have to be considered for diagnosis. Each of these fault models will add substantial run time overhead to diagnosis making the yield analysis process longer. This paper proposes a new approach to perform diagnosis with all the newer fault models in a tractable time. Proposed approach allows simpler addition of newer fault models with marginal run time overhead. Experimental results indicate up to 2.97X run time reduction with proposed approach.