Optimization of the drain-side configuration in ESD-protection SCR-LDMOS for high holding-voltage applications

A conventional silicon-controlled rectifier integrated into a laterally diffused MOSFET (SCR-LDMOS) is studied through 2D TCAD simulations in order to obtain the maximum holding voltage without increasing the area consumption or degrading the power-to-failure robustness. A reference device with 150V trigger voltage, 3V holding voltage and an approximate thermal breakdown at 30 mA/ μ m is adopted. Different configurations of the drain-side region are compared, with the best solution showing a 5x improvement on the holding condition without a significant variation on the other figures of merit. • Tunable holding voltage is a key element for future self-protecting ESD cells. • 2D TCAD simulations are used to address the role of the NBL isolation on the holding regime and thermal runaway. • SCR-LDMOS for high holding voltage are investigated providing the relevant physical understanding. • A preliminary analysis of the very-fast TLP characteristic and of the dynamic voltage overshoot under very fast rising time are presented.