Analysis of Nanoscale Short Channel Effects in Cylindrical Gate-All-Around Junctionless FETs and Performance Enhancement with GaAs and III–V Materials for Low-Power, High Frequency Applications

With the advancement of the semiconductor industry into the sub-10 nm regime, high-performance, low-energy transistors have become important, and gate-all-around junctionless field-effect transistors (GAA-JLFETs) have been developed to meet the demands. Silicon (Si) is still the dominant semiconductor material, but other potential alternatives, such as gallium arsenide (GaAs), provide much higher electron mobility, improving the drive current and switching speed. In this study, our contributions include a comparative analysis of Si and GaAs-based cylindrical GAA-JLFETs, using threshold voltage behavior, electrostatic control, short channel effects, subthreshold slope, drain-induced barrier lowering, and leakage current as the metrics for performance evaluation. A comprehensive analytical modeling approach is employed, solving Poisson’s equation and utilizing numerical simulations to assess device characteristics using the ATLAS SILVACO tool under varying channel lengths and gate biases. Comparisons between Si and GaAs-based devices show what trade-offs exist and what the material engineering strategies are to use the advantages of GaAs while minimizing some disadvantages. The results of the study are a valuable contribution to the design and optimization of next-generation FET architectures, pointing the direction for enabling next-generation beyond CMOS technology.