Approximate Parallel Compressor Design based on Majority Logic

Emerging technologies in digital circuit design increasingly demand methods that optimize performance while minimizing resource usage. Approximate computation (AC) is one such method that sacrifices precision for simplified architecture. In this paper, we investigate the Majority Logic (ML)-based AC design as a promising approach to optimizing circuit performance for next-generation nanotechnologies. We present three high-performance Majority Logic Approximate Parallel Compressors (MLAPC). Notably, the most streamlined MLAPC comprises just a single inverter (Inv), offering significant advantages in hardware cost and delay over earlier designs while retaining high levels of accuracy. Additionally, we developed an unsigned multiplier circuit leveraging the proposed MLAPC. When compared to previous ML multiplier architectures, this new design achieves approximately 29.6% and 40.2% reductions in both the Normalised Mean Error Distance (NMED) and the Maximum Absolute Error (MAE), respectively. Moreover, it lowers the number of required Majority Logic gates (Maj) and decreases delay(D) by 45% and 16.7%, respectively, resulting in remarkable gains in both accuracy and hardware efficiency. Finally, applying the proposed multiplier in MATLAB for image multiplication yields a Structural Similarity Index of at least 0.94 and a Peak Signal-to-Noise Ratio of no less than 31 dB, evidencing its high accuracy.