A Deeply Pipelined 64-bit Multiplier for High-Performance RISC-V Processors
The multiplier is an important component of the processor's computing unit. Multiplication, multiplication, addition, and multiplication and subtraction operations are widely used in various signal processing algorithms. Based on this, this article extends the multiplication instructions of RISC-V, designs a 64-bit multiplier that combines the booth2 algorithm and wallace compression technology, and designs a deep pipeline mechanism for the multiplier to improve performance. Finally, Through logical simulation and emulation, the result output is correct. Comprehensive results show that under the 28nm cmos process, the MAC unit can reach 2.22Ghz.
Authors
- Feng Hu (ORCID: https://orcid.org/0000-0003-2088-6227)
- Xin Niu (ORCID: https://orcid.org/0000-0002-9396-7688)
- Bangjian Xu (ORCID: https://orcid.org/0000-0001-5348-2507)
- Wenyi Liu (ORCID: https://orcid.org/0000-0002-7021-5854)
- Guilan Li
Institutions
- Hunan University (CN)
- National University of Defense Technology (CN)
Publication Details
- Published
- 2024-12-13
- DOI
- https://doi.org/10.1109/icftic64248.2024.10913181
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00