FPGA and GDS II Performance Comparison of Chess Clock Design

In this paper, detailed design of Chess Clock using a Finite State Machine (FSM) is presented. The chess clock design is realized through both Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) flows. This work outlines the complete design process from system conception in Verilog HDL to the final GDS II layout. The FPGA implementation was carried out using Xilinx ISE tool while the ASIC flow was achieved with Cadence design tools, culminating in the generation of a GDS-II file. Through rigorous simulation, synthesis, and optimization, we demonstrated the functionality and efficiency of the Chess Clock FSM. Along with the FPGA and GDSII (layout) implementation, the performance parameters of both are compared in this paper.