An Enhanced Approximate Multiplier Using Error Report Propagation Full Adders

Approximate computing techniques are essential for achieving low-power consumption in error-tolerant applications. This paper presents a novel design for a (3,3:2) compressor-based 8-bit approximate multiplier utilizing Error Report Propagate Full Adders (ERPFAs). Our proposed architecture integrates ERPFAs to enhance computational efficiency while maintaining a cceptable a ccuracy. Extensive simulations demonstrate that the new design achieves a 4.33% reduction in area, a 5.8% reduction in power consumption, and a 43% decrease in delay compared to the existing design. These improvements make the design highly suitable for applications such as image processing and machine learning. The proposed multiplier design strikes an optimal balance between performance and power efficiency, marking a notable advancement in the field of low-power digital circuits.