Low Voltage Feedback Based Folded Flipped Source Follower for Wide Operating Range

In this paper, a novel cascoded-based folded flipped source follower (CFFSF) with a super transistor stage is presented. The CFFSF circuit demonstrates excellent DC transfer characteristics, with the output voltage accurately tracking the input voltage over a specified range. A folded transistor provides an alternative path for sourcing current, enabling the achievement of the desired low output resistance. The inclusion of the super transistor stage enhances both the input and output voltage swing of 0.42V and 0.278V while significantly reducing output resistance of 166Ω. The presented CFFSF architecture has been designed in Cadence Virtuoso Analog Design Environment (ADE) using United Microelectronics Corporation (UMC) 180 nm Complementary MOS technology with a dual power supply voltage of ±0.5V.

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Publication Details

Published
2024-12-06
DOI
https://doi.org/10.1109/wiecon-ece64149.2024.10914719
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.18
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article

Low Voltage Feedback Based Folded Flipped Source Follower for Wide Operating Range

Divyang Rawal, Astha Dadheech, Nikhil Raj
1 citations
Analog and Mixed-Signal Circuit Design
0.18
article

Low Voltage Feedback Based Folded Flipped Source Follower for Wide Operating Range

Divyang Rawal, Astha Dadheech, Nikhil Raj
article en
1 citations

Abstract

In this paper, a novel cascoded-based folded flipped source follower (CFFSF) with a super transistor stage is presented. The CFFSF circuit demonstrates excellent DC transfer characteristics, with the output voltage accurately tracking the input voltage over a specified range. A folded transistor provides an alternative path for sourcing current, enabling the achievement of the desired low output resistance. The inclusion of the super transistor stage enhances both the input and output voltage swing of 0.42V and 0.278V while significantly reducing output resistance of 166Ω. The presented CFFSF architecture has been designed in Cadence Virtuoso Analog Design Environment (ADE) using United Microelectronics Corporation (UMC) 180 nm Complementary MOS technology with a dual power supply voltage of ±0.5V.

LNM Institute of Information Technology (IN)
Affordable and clean energy
Openalex Percentile: Top 49%
Analog and Mixed-Signal Circuit Design
0.18
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