Design Technology Co-Optimization of High-Density RRAM Array for Advanced CMOS Technology Node

In this work, we present a novel n transistor m resistor (nTmR) design that addresses the density limitations of the one-transistor-one-resistor (1T1R) array. The optimal design of nTmR (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n} = 3$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${m} = 2$ </tex-math></inline-formula>) achieves a record-low cell area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.0525~\mu \text {m}^{{2}}$ </tex-math></inline-formula> in the 40-nm technology node. Fabricated using a commercial 40-nm foundry logic process, the nTmR array demonstrates excellent reliability, including an endurance of 100000 cycles and a retention capability of 10 years at 150 °C. Furthermore, the proposed 3T2R array is compatible with FinFET technology nodes, enabling even greater density enhancements. This work offers a promising and practical solution for increasing resistance random access memory (RRAM) density with logic processes, facilitating cost-effective, high-performance embedded memory and computing applications.