A Novel Impedance-Decoupled Gate-Drive Scheme for DC Solid-State Circuit Breakers With High Switch Current Utilization Ratio

This letter presents a novel impedance-decoupling based gate-drive scheme for dc solid-state circuit breakers (SSCBs) targeting ultrahigh fault d<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i>/d<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> protection in densely configured dc grids. There are two major contributions. First, by separating gate-drive impedance for different sections of the solid-state switch turn-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> process, the fault response speed of the SSCBs is significantly accelerated. Second, the proposed decoupled high/low impedance gate drive significantly enhances main switch current utilization while maintaining a low transient voltage overshoot, which can reduce parallel solid-state switch count when handling high d<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i>/d<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> faults in dc grids. Working principles and design guidelines are demonstrated in detail in this letter, and a 4-kA fault interruption experiment is conducted to verify the effectiveness of the novel impedance decoupled gate drive scheme. The experimental results show an ultrahigh main switch current utilization ratio of 96.8% at 1-kA/μs fault d<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">i</i>/d<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i>.