A Comparison of 163‐Bit Hybrid Karatsuba Multiplier and Word‐Serial Multipliers for <scp>ECC</scp> Processors

ABSTRACT Elliptic Curve Processors (ECP) are used for high performance in hardware implementation. The finite field multiplier, which occupies the maximum area in the ECP structure, plays an essential role in deciding its size and performance. The resource‐constrained IoT devices employed in real‐time applications demand the design of a compact yet fast multiplier. In this paper, a Hybrid Karatsuba Multiplier (HKMul) for GF (2 163 ) is proposed for use in Elliptic Curve Cryptography (ECC). It is a sub‐quadratic multiplier. A Word‐Serial Multiplier (WSMul) for the same ECP is also re‐implemented in this work. Both multipliers are synthesized using Xilinx PlanAhead software. A detailed comparison has been presented using different Xilinx Field Programmable Gate Arrays (FPGAs) for detailed comparison. The HKMul nearly matches the WSMul in resource consumption and outperforms it in performance. HKMul outperforms WSMul in two instances, on Spartan‐3 and Virtex‐7, with very small differences of 3.3% and 1.6%, respectively. As the WSMul has a very small delay, it uses 4 clock cycles to generate the multiplication. Hence, HKMul comes out 1.01 to 1.63 times faster than WSMul.