Performance Comparison of Machine Learning Classifiers for FPGA-Accelerated Surface Defect Detection

This research paper presents the results obtained for surface defect detection on metal clamps and classifying defective and defect-free metal clamps using object detection on the PYNQZ2 FPGA development board. The object detection algorithms used in this experiment are the Haar cascade classifier and the Local Binary Pattern (LBP) classifier. The results are compared while performing the classification using the processing system alone. Also, while using the FPGA hardware accelerator, the performance of both classifiers is compared. The experiment aims to assess the impact of hardware acceleration, specifically by including programmable logic, on processing time and resource utilization. The results demonstrate the advantages of employing hardware acceleration through the programmable logic in object detection. The system achieves remarkable reductions in CPU and wall time, significantly improving processing speed while maintaining detection accuracy.