Design and performance analysis of a single-source cascaded H-bridge multilevel inverter with switched rectifier

Abstract MLIs provide better performance than traditional two-level inverters due to reduced harmonic distortion, reduced electromagnetic interference, and increased AC output voltage at lower voltages, but MLIs have a shortcoming such as increased source count. This paper proposes a new topology combination using Switched Rectifier (SR) and High Frequency Link (HFL) that compensates for the increased source count. With this variation, the Cascaded H-Bridge (CHB) MLI, which produces 27 levels with 16 switches, is configured with SR, and the output level is increased to 33. The proposed topology, which can produce outputs with varying frequency and amplitude, is confirmed using the Genesys-2 FPGA development board in both simulation and experimentation. The Nearest Level Control method, which targets low switching frequency, is used to minimize energy losses and reduce total harmonic distortion. Total standing voltage (TSV), cost factor per level, and efficiency calculations are performed to assess the proposed inverter’s economic feasibility. These results are then compared with those of many studies that use HFL in terms of component count, TSV, cost factor and it is noted that the results are like counterpart MLI topologies. Although TSV and cost factor per level are similar, the increase from 27 levels to 33 levels with 1 switch is seen as a significant increase.