Density and energy level of near-interface trap estimated by analysis of threshold voltage shift due to positive bias stress in GaN planar MOSFETs with SiO₂ gate dielectric

Abstract Bias voltage and temperature dependence of positive shift of threshold voltage ( V TH ) by applying positive bias stress to GaN planar-gate metal-oxide-semiconductor field-effect transistors with gate dielectric (SiO 2 ) formed by remote-plasma-assisted chemical vapor deposition were investigated. The V TH shift increased with increasing bias voltage. Stress-time dependence implies trapping of electrons by near-interface traps via tunneling process. V TH shift was theoretically calculated by using a proposed tunneling model considering thermal distribution of electrons in the channel as well as energetic distribution of traps. By good fitting analysis, trap energy level of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" overflow="scroll"> <mml:msub> <mml:mrow> <mml:mi>E</mml:mi> </mml:mrow> <mml:mrow> <mml:mi mathvariant="normal">C</mml:mi> </mml:mrow> </mml:msub> </mml:math> + 0.78 eV and trap concentration of 2–8.5 × 10 12 cm −3 were obtained.