A 4-Bit 1.4 GS/s Self- Calibrated Flash ADC with Low-Leakage Power in 0.25μM CMOS

This paper presents a 4-bit 1.4[Formula: see text]GS/s Self[Formula: see text]Calibrated Flash ADC with low leakage power using a 0.25[Formula: see text] [Formula: see text]m CMOS VLSI circuit. In order to eliminate the cause of bubble code errors, a Direct Bubble Error Controller (DBEC) block is used after a set of low-leakage power comparators known as Sleep Transistor-based NAND Linear Tunable Transconductance Element (ST-NAND-LTE) as the first step. This approach results in a 93.12% power reduction and a 66.35% delay reduction compared to the conventional comparator technique. Finally, the MPTL (Multiplexer Pass Transistor Logic) Encoder reduces the transistor count by 47.61% compared to the Dynamic Priority Encoder and circuit complexity prescribed for Flash ADC. T-Spice was used to simulate the 4-bit SC-FADC schematic circuit, which was implemented using S-Edit in the 0.25[Formula: see text][Formula: see text]m CMOS Tanner EDA Tool. The resulting parameters exhibit 3.77 ENOB with a power utilization of 2.19[Formula: see text]mW and 0.321[Formula: see text]pJ/conv. -step FOM at 1.5[Formula: see text]V supply.