SYSTEM-ON-A-CHIP AND IP-CORES VERIFICATION FLOW: ANALYSIS OF OPPORTUNITIES FOR AUTOMATION

The main point of this paper is a deep review of automation possibilities in SoC and IP-cores verification process. The verification process takes a great effort and spends a lot of time in the common process of IC development. And that flow is too complex to allow hard formal ways for resolving. So any verification engineer tries to implement some automations steps to speed up the verification process. And there are a lot of CAD tools which should help in that. However, the CADs provided by the “big 3” only cover selected steps in the verification process, so there is a need to identify route steps that are not covered by the CADs. This article presents a review of all stages of the verification route in terms of the possibility of automating each stage or all flow. Main stages of the verification process will be observed and analyzed. Existing CAD tools which cover some stages and a “white spaces” in automation flow will be pointed. Methods of automation verification process also will be observed. Most popular of them are reusing, generation from template, format methods, LLM-models and so on. Possible advantages from each of them for each verification stage will be analyzed. Also the verification process as flow will be analyzed to detect most work consumption stages and develop recommendations for possible methods to reduce it. The article is aimed at systematization of knowledge on the verification of SoC and IP-cores area and finding of promising directions of verification automation development.