Development of a Clock and Data Recovery (CDR) ASIC for heavy-ion physics experiments

Abstract The Heavy-Ion Research Facility in Lanzhou (HIRFL) and the High Intensity heavy-ion Accelerator Facility (HIAF) are essential platforms for heavy-ion scientific research in Asia. These experimental facilities aim to enhance advanced experimental conditions for research in heavy-ion physics and related interdisciplinary fields. In the context of large-scale scientific experimental facilities, higher demands have been proposed on the radiation resistance and transmission speed of the transmission links. The clock and data recovery (CDR) circuit is one of the core circuits of the high-speed transmission links. It can extract the clock information from high-speed serial data and recover the clock for sampling optimally at the center of a unit interval (UI), improving the quality of data transmission in physical experiments. This paper presents a 20 Gbps CDR ASIC in a 55 nm CMOS technology, aiming for data transmission in physics experiments. It is based on a quarter-rate architecture. The area of the core CDR is 0.226 mm 2 , and the power efficiency is 13.53 pJ/bit with a supply voltage of 1.2 V. The irradiation tolerance of the CDR is improved through radiation-hardened by design (RHBD) techniques and triple-mode redundancy (TMR) at critical nodes.