Strain- and dipole-induced interface states in gate-all-around transistors: Properties and implications for application

Gate-all-around architecture provides the ultimate solution for controlling carriers in ultrascaled transistors. However, the complex all-around interface between $\mathrm{Si}$ and amorphous ${\mathrm{Si}\mathrm{O}}_{2}$, especially at the inevitable corners, becomes detrimental to device performance. Here, we endeavor to unveil the properties of interface and corner states in gate-all-around field-effect transistors (GAAFETs) by first building real all-around interfaces between silicon and amorphous ${\mathrm{Si}\mathrm{O}}_{2}$, and then conducting large-scale (up to 2796 atoms) first-principles calculations on them. Results show that the interface states are not only contributed by the widely known dangling bonds, but also by the scarcely recognized corner strains and interface dipoles. They present asymmetric densities near the conduction and valence bands, and show distinct spatial distributions across the channel cross section. Fortunately, the interface states turn out to be tunable by changing the channel size, orientation, and geometry. This research is very meaningful because it can explain several experimental observations, including the performance degradation of sub-4-nm channel devices, the extremely low hole mobility in GAAFETs, the degradation of drain-induced barrier lowering in small-size GAAFETs, and the superior performance of nanosheet channels over nanowire ones. Based on these results, it is suggested that we should pay special attention to the quality of corner interfaces during device fabrication, and keep focusing on nanosheet GAAFETs instead of nanowire ones at this stage.