Effect of Wafer Backside Thin Film Thickness on Wafer Stealth Dicing Performance
The growing need for thinner, smaller die sizes with high die strength and low cycle times has allowed for stealth dicing to become an increasingly popular die singulation method. However, its process margins are relatively new and there are few studies documenting the relationship with laser irradiation during stealth dicing and silicon integrity. A pre-dicing wafer grinding process is commonly used during the SDBG process to ensure sufficient polishing and planarity as well as to remove any thin films or artifacts formed during wafer fabrication. However, this pre-grinding step increases manufacturing costs and cycle times. Thus, this study focusses on studying the effects of thin films on the wafer backside (non-metal, silicon) on the modified layers form during SD and the feasibility in removing a pre-dicing wafer grind process.
Authors
- Dao Kun Lim (ORCID: https://orcid.org/0000-0002-5499-1407)
- Haobijam Johnson Singh (ORCID: https://orcid.org/0000-0002-5387-7549)
- Kian Guan Khoo
- Ming‐Chun Lu (ORCID: https://orcid.org/0000-0001-5293-0718)
- Ankur Harish Shah (ORCID: https://orcid.org/0000-0001-8206-7943)
- Rommel Tanola
- Wen How Sim
- Nathaniel Simon George
- Tey Jie Lin Jolyn
Institutions
- Micron (United States) (US)
Publication Details
- Published
- 2024-12-03
- DOI
- https://doi.org/10.1109/eptc62800.2024.10909678
- Citations
- 1
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.21