Semiconductor Chip and Package Co-Design and Assembly for Dual Use in Flip Chip and Wirebond BGA Packages
Semiconductor packaging technology has developed significantly since the 1970s when the first Wire-bond Ball Grid Array (BGA) packages were introduced. In the 1990s, the first Flip-Chip BGA packages were developed. In most case, BGA packages utilize two primary methods to connect the silicon die to the substrate: Wire-bond and Flip-Chip. In this study, a design and assembly method is shown that enables assembly of the same die into a 15mm Wire-bond BGA package and a 9.4mm over-molded FCBGA package with almost the same IO outputs. The die that is used for this study is designed in 28nm technology. Furthermore, since the die is “flipped” in the flip-chip package compared to the wire-bond package, the die, package, and printed circuit board designs must all be considered concurrently to enable the best system solution for both packages. For 15mm Wire-bond BGA package, after wafer singulation, the die is directly bonded to the substrate using die attach material with the active side of the die facing “up”. The die pinouts are connected to the substrate via Wire-bonding process and then followed with Molding process and ball attach process for BGA outputs. For 9.4mm Flip-Chip BGA package, to enable the die to convert from Wire-bonding package to flip-chip package, firstly we need to create bumps over the original wafer. In this study, we use redistribution layers to spread the peripheral bond pads to new connection bumps over the die surface. After the bumping process and wafer singulation process, the bumped die is flipped and attached to the substrate with the active side of the die facing “down”, the solder cap in top of the bumps serves as the connection material. The following steps are molding and BGA Ball attach process. The key challenges are bumping quality, die-attach accuracy, and molded underfill void underneath the die. In this study, the inline check for bumping, die attach and molding show the process is stable and meets the requirements. The paper present package design, assembly process and reliability performance of both packages.
Authors
- Meijiang Song
- Trent Uehling
- Kaelin Wang
- Robert Lo
- You Ge (ORCID: https://orcid.org/0000-0002-8374-7366)
- Te‐Hua Fang (ORCID: https://orcid.org/0000-0002-7032-3193)
- Azham Mohd Sukemi
- Rongrong Jiang (ORCID: https://orcid.org/0000-0002-5339-2517)
- Bihua He
- Tingdong Zhou (ORCID: https://orcid.org/0009-0002-2949-8706)
Publication Details
- Published
- 2024-12-03
- DOI
- https://doi.org/10.1109/eptc62800.2024.10909878
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00