Splitting Process Integration for 2.5D/3D Packaging
To reduce packaging cost, 300mm Si wafer transferred on molding material was evaluated and demonstrated through splitting approach. Chip to wafer stacking, molding and splitting with dummy HBM and CPU/GPU were achieved after process optimization. Metal lines fabricated by damascene approach were used to study the splitting process effect.
Authors
- W. Schwarzenbach (ORCID: https://orcid.org/0000-0003-2821-0854)
- Vasarla Nagendra Sekhar
- Guillaume Besnard (ORCID: https://orcid.org/0000-0003-2275-6012)
- Bich-Yen Nguyen (ORCID: https://orcid.org/0000-0003-4347-4583)
- Hongyu Li (ORCID: https://orcid.org/0000-0002-3564-6069)
- Sharon Pei-Siang Lim
- Nadia Ben Mohamed
Institutions
- Soitec (France) (FR)
- Agency for Science, Technology and Research (SG)
- Institute of Microelectronics (SG)
Publication Details
- Published
- 2024-12-03
- DOI
- https://doi.org/10.1109/eptc62800.2024.10909763
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00