Multi-RF Chip Module Through FOWLP

This paper depicts the development of multiple Pseudomorphic high electron mobility transistor (pHEMT) semiconductors with AlGaAs/InGaAs/GaAs developed to realize high power and high-efficiency amplifiers for System-in-Package (SiP) modules. The developed Fan-out package measures 5.27mm X 7.15 mm X 0.15mm, based on the electrical simulation has anticipated gain of approximately 3-4dB, with power consumption < 1-1.5 W. The Re-distribution Layer (RDL) is introduced onto the Au pads at the frontside of the FOWLP to establish interconnections between the respective III-V chips, implementing Under Bump Metallization (UBM) and completes the package with solder bumps, for mounting onto the Printed Circuit Board (PCB). The package consists of four RF chips with dies of 50um and 100um die-thicknesses. On the back of the FOWLP, a copper ground plane is plated to build interconnections from the back of the embedded chips through the Though-Mold-Vias (TMVs) to the top of the package, that was introduced to aid heat dissipation when the SiP is turned on.

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Publication Details

Published
2024-12-03
DOI
https://doi.org/10.1109/eptc62800.2024.10909941
Citations
3
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
0.63

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article

Multi-RF Chip Module Through FOWLP

Chia Lai Yee, Hsiao Hsiang Yao, Sharon Lim Pei Shan, Jacob Soh et al.
3 citations
Radio Frequency Integrated Circuit Design
0.63
article

Multi-RF Chip Module Through FOWLP

Chia Lai Yee, Hsiao Hsiang Yao, Sharon Lim Pei Shan, Jacob Soh, Serine Soh Siew Boon, David Ho Soon Wee, Norhanani Jaafar, Feng Xu, Chan Kien Teck, Ong Poh Kuan
article en
3 citations

Abstract

This paper depicts the development of multiple Pseudomorphic high electron mobility transistor (pHEMT) semiconductors with AlGaAs/InGaAs/GaAs developed to realize high power and high-efficiency amplifiers for System-in-Package (SiP) modules. The developed Fan-out package measures 5.27mm X 7.15 mm X 0.15mm, based on the electrical simulation has anticipated gain of approximately 3-4dB, with power consumption < 1-1.5 W. The Re-distribution Layer (RDL) is introduced onto the Au pads at the frontside of the FOWLP to establish interconnections between the respective III-V chips, implementing Under Bump Metallization (UBM) and completes the package with solder bumps, for mounting onto the Printed Circuit Board (PCB). The package consists of four RF chips with dies of 50um and 100um die-thicknesses. On the back of the FOWLP, a copper ground plane is plated to build interconnections from the back of the embedded chips through the Though-Mold-Vias (TMVs) to the top of the package, that was introduced to aid heat dissipation when the SiP is turned on.

Agency for Science, Technology and Research (SG), Institute of Microelectronics (SG), Medical Technologies (Czechia) (CZ)
Agency for Science, Technology and Research
Affordable and clean energy
Openalex Percentile: Top 30%
Radio Frequency Integrated Circuit Design
0.63
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Multi-RF Chip Module Through FOWLP — Chia Lai Yee, Hsiao Hsiang Yao, et al. · (2024) | TGRS Research Map | TGRS