Signal Integrity Analysis of Dense Wire Channels on 2.5D Substrate Technologies for UCIe Applications

This paper systematically analyzes the impact of various physical design parameters on the signal integrity performance of 2.5D advanced packaging platforms with two types of redistribution layers Fan Out Wafer Level Packaging (FOLWP) and Silicon Interposer built using BEOL - when Universal Chiplet Interconnect Express (UCIe) die to die interfaces are implemented. The specifics of the wires, such as their density, maximum length, impedance characteristics and how they are realized vary with the packaging technology, hence the design will change depending on the technology used. The impact of parameters such as line width, line to line spacing, metal thickness, dielectric thickness as well as routing configuration has on the performance of the digital channel is discussed in this work. The emphasis is on the limiting cases for each technology. The minimum achievable width, metal thickness and dielectric thickness for the two RDL technologies (FOWLP and BEOL) discussed here are different and they have large implication on the performance of the digital channel especially when 32Gbps per wire signal as defined in the UCIe are to be used.