Electrical Characterization and Reliability Studies of Through SI Interposer (TSI) with 5-Layer Frontside Cu Metal and 2-Layer Backside Cu RDL

To realize high-performance computing like artificial intelligence (AI) and Internet of Things (IoT), Through Silicon Interposer (TSI) is one of the crucial technologies among 2.5D/3D platform. For enhancing the system performance, it has become a trend to build more metal layers on the wafer frontside and backside of TSI wafers. We have previously demonstrated TSI process with 5-layer frontside Cu metal and 2-layer backside Cu Redistribution Layer (RDL). However, more electrical data is required to verify the quality of the process. In this work, we conducted reliability tests for the TSI wafers including (1) Thermal Cycling (TC) from -40C to 125C with 150, 500, 750, 1000 cycles, (2) High Temperature Storage (HTS) at 125C with 250, 500, 750, 1000 hours and (3) Unbiased Highly Accelerated Stress Test (uHAST) at 130C, 85% RH with 96 hours. The reliability results had validated the robustness of the TSI fabrication process.