Thermal Test Vehicle for Transient Thermal Characterization of Large Body Size Chips

Thermal management is becoming an ever more critical challenge for high performance computing (HPC) chips as the power density and chip size increase. For heterogeneous integration with multiple chiplets and very large body size in the package, the characterization of the thermal behavior becomes even more challenging. This paper describes a design practice using Thermal Test Chips (TTC) and Thermal Test Vehicles (TTV) which can accurately emulate the heating power distribution of a real functional chip, providing the capability for configurable power distribution and in situ temperature measurement on the chip. The TTC on the TTV features a design incorporating an array of heating zones, each equipped with in situ temperature-sensing diodes. With the array design of the TTV, we can configure the heating zones to our preference, thereby simulating either uniform heating or “hot spots”. Various test items can be measured based on a flip chip ball grid array (fcBGA) TTV integrated with a liquid cooled cold plate in accordance with the TTV design. By utilizing the temperature sensing diodes situated at various points throughout the TTC, we can ascertain the comprehensive temperature distribution (transient and steady state) across the TTC. Furthermore, the transient thermal characterization can be performed by selecting specific sensing diodes to obtain the thermal impedance (Zth) curve and structure function. The thermal resistance from junction to case <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\theta_{\text{JC}})$</tex> and from junction to ambient <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\theta_{\text{JA}})$</tex> can also be characterized under different conditions of thermal interface materials (TIMs) and coolant flow rates. Based on various experimental results, we have demonstrated that the TTV design is suitable for the thermal characterization of large-body-sized chips. It will be useful for a comprehensive and in-depth understanding of the on-die and package level heat dissipation behavior, which can be used for characterization and optimization of real-chip thermal performance.