A Novel Approach to Reduce Impedance Discontinuities for High-speed Channel in IC Packages

With the increasing operating frequency of high-speed signals nowadays, challenges are rising to ensure a good quality of signal transmission along the entire signal channel. In integrated circuit (IC) package design, one must take good care of various segments - planar signal traces, as well as vertical interconnects, namely vias and ball grid array (BGA) balls. In general, both vias and BGA balls are considered as impedance discontinuities in the signal path, and both could significantly deteriorate high-speed signal quality at high frequencies. This paper presents a novel approach to reduce impedance discontinuity in high-speed channels in IC packages, with a focus on vias and BGA balls of single-ended signal nets. Extra inductance is introduced to compensate for the capacitive loading from the pads of vias and BGA balls. With the new approach, characteristic impedance is well controlled around vias and BGA balls to stay close to the system requirement, thus the electrical performance is comparable if not superior to the conventional approach. Meanwhile, chipmakers benefit from our new approach not only by keeping more space/layers for signal trace routing, but also by achieving better packaging reliability.