Chip to Wafer and Wafer to Wafer Density Estimation and Design Rules Physical Verification

Hybrid bonding, an essential method for integrating diverse packages, offers significant opportunities for pushing the boundaries of pitch scaling in semiconductor technologies. As 3D nodes evolve, it's crucial to investigate new materials and processes to keep pace with these advancements. In this work, we analyze the design rule check and estimate the layer pattern density part of the design that has test structures such as comb, serpentine, daisy chain, kelvin, modified kelvin and meander for chip to wafer (C2W) and wafer to wafer (W2W) bonding.

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Publication Details

Published
2024-12-03
DOI
https://doi.org/10.1109/eptc62800.2024.10909894
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

Chip to Wafer and Wafer to Wafer Density Estimation and Design Rules Physical Verification

Rahul Dutta, Vasarla Nagendra Sekhar, Cheemalamarri Hemanth Kumar, R. Mani
3D IC and TSV technologies
article

Chip to Wafer and Wafer to Wafer Density Estimation and Design Rules Physical Verification

Rahul Dutta, Vasarla Nagendra Sekhar, Cheemalamarri Hemanth Kumar, R. Mani
article en

Abstract

Hybrid bonding, an essential method for integrating diverse packages, offers significant opportunities for pushing the boundaries of pitch scaling in semiconductor technologies. As 3D nodes evolve, it's crucial to investigate new materials and processes to keep pace with these advancements. In this work, we analyze the design rule check and estimate the layer pattern density part of the design that has test structures such as comb, serpentine, daisy chain, kelvin, modified kelvin and meander for chip to wafer (C2W) and wafer to wafer (W2W) bonding.

Agency for Science, Technology and Research (SG), Institute of Microelectronics (SG)
Agency for Science, Technology and Research
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Openalex Percentile: Top 74%
3D IC and TSV technologies
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