Live Thermal Simulation Using Digital Twin for Efficient Semiconductor Layout Design

This paper presents a novel approach for rapid thermal assessment of electronic devices using a Reduced-Order Model (ROM) based digital twin, with specific application to Electric Vehicle (EV) drivetrain inverters. The method utilizes Singular Value Decomposition (SVD) to construct a computationally efficient model that enables real-time manipulation of chip layouts and instant visualization of thermal impacts. Tested on both homogeneous and heterogeneous chip configurations, the approach demonstrates high accuracy with maximum temperature differences of ~3 K compared to Computational Fluid Dynamics (CFD) simulations and significant computational efficiency (results generated in ~1 second). This technology offers a powerful tool for balancing increased power density demands with effective thermal management, potentially accelerating the development of high-performance EV drivetrain inverters.