Analysis of Substrate Trace Cracking in Combined Power and Thermal Cycling Reliability Test

Combined power and thermal cycling (PTC) test is one of the key automotive industry requirements. It is a stringent reliability condition and is seen to induce few early fails in the substrate traces. The temperature distribution within the package is non-uniform and varies with both chip power and ambient temperature requiring complex multi-physics based analysis. This study uses a sequentially coupled thermal-mechanical simulation methodology to analyze substrate trace crack failure mode in PTC. The reliability of substrate traces in PTC is compared to pure thermal cycling test condition. Further, the effect of heat transfer coefficient, number of power cycles, trace width and solder mask material on trace reliability is analyzed. Testing data is used to validate the modeling results.