Novel PG IO Buses Architecture with Bond Wires to Reduce IO Buses Resistance and Provide EMI Shield

As semiconductor technologies shrink, challenges such as increased IO bus resistance, IR drop, and electromagnetic interference (EMI) become critical, especially with the reduction of Power/Ground (PG) pins. These issues are exacerbated by the need to integrate more general-purpose IO (GPIO) pins. This paper proposes a novel PG IO Bus Architecture with parallel bond wire structures at the die edge. The proposed architecture reduces IO bus resistance, improves IR drop performance, and enhances Power Integrity and Signal Integrity (PISI) while also providing EMI shielding. Additionally, the reduction in PG pins allows for increased GPIO functionality. This paper contributes a scalable solution for improving SoC design in advanced technology nodes.