Trade-off Between Chiplet Dimensions and Packaging Parameters for Optimal Performance to Cost for Chiplet Based Heterogeneous Integration

Chiplets are small, modular integrated circuits that work together to offer advantages over traditional monolithic chips. They are made by partitioning a monolithic chip into functional components, densely interconnected using standardized interfaces. However, such interfaces introduce additional terminals into the chiplet (usually at chiplet periphery) increasing area and power utilization per chiplet to meet bandwidth and performance targets. Moreover, such interfaces do not (yet) support on-chip like wiring pitches due to input/output design and manufacturing constraints. These trade-offs must be considered while optimizing for partitioning a large chip into chiplet-based heterogeneous systems. By modeling such factors as a function of the number of chiplets and pitch of terminals between chiplets, one can optimize the performance-to-cost of the entire system. In this paper we consider a simple multi-core (e.g. GPU based) large chip and partition it into smaller chiplets. We account for the increased overhead of the portioning - mainly the communication between chiplets - which leads to either a performance decrease or power increase but with a concomitant improvement in yield or cost. The cost-performance function is studied as function of chiplet dimensions. We introduce a portioning figure of merit p-FOM to guide the chip architect.