Investigation of the Parasitic Surface Conduction Effect on Interposers for 2.5D/3D Heterogeneous Integration

This paper investigates the impact of dielectric layers and annealing conditions on parasitic surface conduction (PSC) in Silicon-on-Insulator (SOI) interposers designed for 2.FFF integration. By employing coplanar waveguides (CPW s) as test structures, RF transmission losses within interposers fabricated with various combinations of Silicon Nitride <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{SiN}_{\mathrm{x}})$</tex> and Silicon Oxide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{SiO}_{2})$</tex> layers and hydrogen and hydrogen-frannealing have been evaluated. From the findings, it is revealed that incorporating a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{SiNx}$</tex> Layer above the buried oxide in a hydrogen-free <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{H}_{2})$</tex> free environment annealing reduces RF losses. This demonstration in the reduction on transmission loss shows a potential approach to improve the performance of 2.F <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5\mathrm{D}$</tex> integrated circuits.