Reliability Study of Multi-Chip GaN Device by Fan-Out Panel Level Package

In this study, a half-bridge electrical configuration of GaN package, including two GaN chips and two Si chips, were integrated into a 6mmx7mm package using fan-out panel level process. Cu stud was used to modify the die top connection. Three types of reliability evaluation were conducted, including temperature cycle test (TCT), highly accelerated stress test (HAST) and intermittent operating life (IOL) test. Although the package passed 300 cycle TCT test, 20% samples failed at 400 cycles. Delamination was found at the joint location between redistribution copper layer and the copper studs. In addition, delamination also can be found between the GaN chip surface and molding compound, which indicated that the thermal stress of the package was too high, and adhesion force of recent interface was not enough to support higher reliability grade.