Signal Integrity Simulation and Analysis for 2.5D Advanced Package Interconnect Based on Universal Chiplet Interconnect Express (UCIe)

This paper presents the design and signal integrity (SI) simulation of 2.5D advanced packaging interconnects based on the Universal Chiplet Interconnect Express (UCIe) protocol. The study compares multiple interconnect structures, including silicon bridge, wafer-level fan-out packages (WLFOP), and FCBGA substrate interconnect. Using UCIe-defined voltage transfer function (VTF) metrics for loss and crosstalk, the design achieves high-speed 32Gbps transmission with optimized routing patterns and transmission lines. This study offers a new approach for optimizing interconnect designs to meet UCIe standards, balancing signal integrity performance with the constraints of current manufacturing processes. The results provide insights into enhancing performance and scalability in chiplet-based heterogeneous integration systems.