Simulation and Optimization of Low-ESR and Low-ESL Deep Trench Capacitor

As integrated circuits evolve towards higher density, reduced line width, and finer interconnect pitch, the significance of maintaining robust power integrity (PI) and signal integrity (SI) has become increasingly paramount. The strategic placement of capacitors within circuit can aid in preserving standardized voltage level and waveform for both power and signal lines, thereby mitigating the impact of noise and crosstalk and ensuring optimal circuit operation. The effective bandwidth and decoupling efficacy of decoupling capacitors are not solely dependent on their capacitance value but are also influenced by parasitic effects such as equivalent series resistance (ESR) and equivalent series inductance (ESL). In recent years, deep trench capacitor (DTC) technology has garnered significant attention as one of the most promising silicon-integrated capacitor technologies. DTC achieve exceptionally high capacitance density by constructing capacitive structures within deep trenches. Moreover, due to their strong process compatibility and design flexibility, when employed as decoupling capacitors, DTC often require only short interconnect lines to the working points, substantially reducing loop inductance introduced by interconnection. This study employs simulation methodology to investigate the primary sources of parasitic effects in DTC device. Building upon these findings, the research validates a superior multi-terminal wiring approach and capacitor cell layout principle. The results of this work contribute to the development of DTC with reduced parasitic effects while maintaining equivalent capacitance density, thereby facilitating the broader application of it.