Realizing Void-Free Superconducting TSV on Interposer with One-Step Liner-Less Indium

A multitude of research groups have demonstrated interposers with through-interposer superconducting interconnects. In many cases, superconducting interconnects are deposited using standard foundry processes. Despite early success, thin film Ta, Al or TiN film deposition techniques are often slow, thin and require a layer of barrier oxide. The former limits the critical current limit while the latter may cause a two-level defect leading to a loss in superconductivity. In recent times, indium in via has been reported. Yet, in those works, wafer surfaces are often contaminated with indium residues due to the soft and ductile properties of indium which makes it difficult to remove subsequently. In this manuscript, we demonstrate technique to fabricate indium-filled TSVs utilizing a novel direct-deposit technique on 12" wafers. In this case, fully fill TSV deeper than 100μm. Thereafter, the substrate is subjected to annealing temperature above the melting point of indium in an inert environment. Finally, overfill the vias to create bumps for vertical chip to chip and chip to wafer flip chip bonding.

Authors

Institutions

Publication Details

Published
2024-12-03
DOI
https://doi.org/10.1109/eptc62800.2024.10909898
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
0.00

Funders

Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Realizing Void-Free Superconducting TSV on Interposer with One-Step Liner-Less Indium

Haitao Yu, Norhanani Jaafar, Tseng Ya-Ching, Hongyu Li et al.
3D IC and TSV technologies
article

Realizing Void-Free Superconducting TSV on Interposer with One-Step Liner-Less Indium

Haitao Yu, Norhanani Jaafar, Tseng Ya-Ching, Hongyu Li, Meng Keong Lim
article en

Abstract

A multitude of research groups have demonstrated interposers with through-interposer superconducting interconnects. In many cases, superconducting interconnects are deposited using standard foundry processes. Despite early success, thin film Ta, Al or TiN film deposition techniques are often slow, thin and require a layer of barrier oxide. The former limits the critical current limit while the latter may cause a two-level defect leading to a loss in superconductivity. In recent times, indium in via has been reported. Yet, in those works, wafer surfaces are often contaminated with indium residues due to the soft and ductile properties of indium which makes it difficult to remove subsequently. In this manuscript, we demonstrate technique to fabricate indium-filled TSVs utilizing a novel direct-deposit technique on 12" wafers. In this case, fully fill TSV deeper than 100μm. Thereafter, the substrate is subjected to annealing temperature above the melting point of indium in an inert environment. Finally, overfill the vias to create bumps for vertical chip to chip and chip to wafer flip chip bonding.

Agency for Science, Technology and Research (SG), Institute of Microelectronics (SG)
National Research Foundation, Science and Engineering Research Council
Climate action
Openalex Percentile: Top 74%
3D IC and TSV technologies
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Realizing Void-Free Superconducting TSV on Interposer with One-Step Liner-Less Indium — Haitao Yu, Norhanani Jaafar, et al. · (2024) | TGRS Research Map | TGRS