Realizing Void-Free Superconducting TSV on Interposer with One-Step Liner-Less Indium
A multitude of research groups have demonstrated interposers with through-interposer superconducting interconnects. In many cases, superconducting interconnects are deposited using standard foundry processes. Despite early success, thin film Ta, Al or TiN film deposition techniques are often slow, thin and require a layer of barrier oxide. The former limits the critical current limit while the latter may cause a two-level defect leading to a loss in superconductivity. In recent times, indium in via has been reported. Yet, in those works, wafer surfaces are often contaminated with indium residues due to the soft and ductile properties of indium which makes it difficult to remove subsequently. In this manuscript, we demonstrate technique to fabricate indium-filled TSVs utilizing a novel direct-deposit technique on 12" wafers. In this case, fully fill TSV deeper than 100μm. Thereafter, the substrate is subjected to annealing temperature above the melting point of indium in an inert environment. Finally, overfill the vias to create bumps for vertical chip to chip and chip to wafer flip chip bonding.
Authors
- Haitao Yu (ORCID: https://orcid.org/0009-0004-6546-0013)
- Norhanani Jaafar
- Tseng Ya-Ching
- Hongyu Li (ORCID: https://orcid.org/0000-0002-3564-6069)
- Meng Keong Lim
Institutions
- Agency for Science, Technology and Research (SG)
- Institute of Microelectronics (SG)
Publication Details
- Published
- 2024-12-03
- DOI
- https://doi.org/10.1109/eptc62800.2024.10909898
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Research Foundation
- Science and Engineering Research Council